1) Field of the Invention
This invention relates to semiconductor devices and more particularly to an improved metal oxide semiconductor field effect transistor (MOSFET) structure.
2) Description of the Prior Art
As the size of semiconductor devices decrease there have been increasing electrical device performance and manufacturing problems. In semiconductor devices, particularly metal oxide semiconductor field effect transistor (MOSFET) devices, a problem in controlling transistor characteristics develops as the feature size of these devices is reduced below one micron. To continue scaling down, new MOSFET structures have been developed to overcome problems. One such structure, the lightly doped drain (LDD) is a N-channel MOSFET structure often used to comply with hot carrier lifetime criteria for near and submicron MOS technology. However, low electro-static discharge (ESD) failure threshold has been reported on this lightly doped drain (LDD) structure. Moreover, present ESD protection methods focus on safeguarding the inputs against gate oxide damage. Many devices can be used as protection elements for input protection such as resistors, field transistors and bipolars. However, for the output and input/output circuits, the sensitivity to ESD stress is high when the lightly doped drain (LDD) of the MOSFET is directly tied to the output pad (see FIGS. 1A and 1B). Therefore, to reduce ESD stress, a thin gate oxide MOSFET device should be self protected if possible. Thin gate MOSFET's are often formed with lightly doped drain (LDD) structures to met hot carrier lifetime criteria, but this LDD structure has been reported susceptible to low ESD failure threshold. Therefore, there is a need for a new self protected (non-LDD) MOS device structure which is resistant to low ESD threshold failure and does not increase manufacturing costs or complexity.